The following U.S. Pat. Nos. 6,189,132, 6,473,882, 6,507,931, and 6,928,634 are believed to represent the current state of the art. These patents all relate to prior art with respect to the current patent.
The above patents describe techniques to improve the printability of mask photolithography as it pertains to the manufacture of integrated circuits.
Over the past several decades, integrated circuit (IC) manufacturing has been based on the optical pattern transfer process called photolithography. A completed IC design layout is captured in a form of multiple design layers corresponding to various processing steps involved in a formation of semiconductor devices in silicon. Each of the sequential processing steps requires a photomask which captures the circuit patterns of a given design layer (or a combination of several layers). A lithographic imaging system uses the photomask as the master object which image is optically transferred onto the silicon substrate covered with a photosensitive material. The resultant optical image triggers a photochemical reaction, which, after development and etching steps, leads to the formation of the semiconductor device structures.
With the continuing shrinkage of the IC devices, the lithographic process has become increasingly challenging. As circuit pattern dimensions became smaller than the wavelength of light used for their imaging, the optical pattern transfer process approached its fundamental resolution limits and became highly nonlinear. This patterning mode, known as sub-wavelength lithography, led to the emergence of various resolution enhancement technologies (RET) to cope with layout printability problems, which include a variety of issues related to the pattern transfer process. Such problems include but are not limited polygon edge placement errors, pattern distortions, pattern fidelity (i.e. image contrast, slope) reduced pattern tolerance to process variations (i.e. exposure dose, focus, aberrations, etc.), and printability hot spots, which significantly reduce the yield of the integrated circuit.
Optical Proximity Correction (OPC) is a resolution enhancement technology that modifies layout patterns to compensate for the optical and process proximity effects by minimizing the pattern edge placement errors (EPEs), that is to modify the layout patterns so as to minimize the error between the printed edges and the edges of the original layout pattern, typically called the uncorrected edges. In recent years, OPC has become the critical component of the mask data preparation process and is used routinely in the advanced IC manufacturing. Initially, OPC was based on a set of predetermined rules which defined the amount of polygon edge movement needed for a given pattern configuration. However, as the imaging non-linearities and the proximity effects increased, rule-based OPC was no longer sufficient and became replaced by a model-based approach. Model-based OPC technology uses lithography simulation to predict and compensate for the proximity effects. Although computationally more expensive than the rule-based method, the model-based OPC provides superior conversion results and avoids the need for generation of long and complex sets of rules.
As the industry moved into the deep sub-100 nm technology space, new printability challenges emerged. At the 65 nm technology node, even the application of the most advanced lithography technology and OPC tools leaves behind multiple localized layout instances with marginal printability known as hot spots. These hot spots have become one of the biggest limiting factors of the IC yield, and they threaten to become even more dominant of an issue as the industry moves into 45 nm technology and below. The OPC technology alone cannot cope with this problem due to the fundamental limitations of its underlying algorithms. Although OPC is an optimization problem, the existing solutions so far have relied on sub-optimal techniques, where layout polygon segments are individually adjusted, in a sequential order, until the EPE tolerances are met. Generally, this process involves the simulation-based calculation of various localized image properties from which the direction and the amount of movement for each polygon edge is estimated. For example, some of the more advanced OPC methodologies such as described by Granik, et. al. in U.S. Pat. No. 6,928,634 granted Aug. 9, 2005, have been utilizing partial derivative matrices of relevant printability criteria such as mask error enhancement factor (MEEF) to more accurately determine how to move individual polygon edges. Even though the general “trial and error” OPC approach in its various embodiments has worked sufficiently well to minimize the edge placement errors, it has reached its fundamental limitations in terms of the attainable convergence accuracy as well as its extendibility to solve more complex optimization problems.
Due to the limitations of the OPC technology, the industry has pursued various approaches to establish design trade-offs and generate additional or modified designed rules in order to tackle the hot spot printability problem. Such approaches include IC design techniques based on restricted design rules, utilization of layout compaction and other rule-based layout modification technologies.
Restricted design rule (RDR) methodology addresses the printability issues by introducing regularity to the IC layout. This approach allows to determine and eliminate design configurations and relevant rules that yield poor printability results. However, this benefit comes at a price of significantly reduced freedom of the designer to make optimal trade-offs between critical factors such as the circuit performance and area.
Layout modification technologies, such as compaction, have been previously described by Mukai in U.S. Pat. No. 6,473,882, granted Oct. 29, 2002, and some have used compaction to make the IC layout compliant to a set of design rules while minimizing a linear objective function as described by Heng et. al. in U.S. Pat. No. 6,189,132 granted Feb. 13, 2001. More recently, this technology has been adapted to deal with printability problems. Since the compaction technology is based on linear programming (also commonly referred to as linear optimization) combined with heuristic techniques, it requires linearization of the problem of interest. For example, printability hot spots can be addressed through the iterative modification of relevant design rules and the use of compaction to perturb the layout as described by Kotani et. al. in U.S. Pat. No. 6,507,931 granted Jan. 14, 2003. However, the application of such methodologies is very difficult due to the complexity associated with determining of how to modify the design rules to improve the printability.
The main reason why it is difficult to solve printability problems with the above mentioned technologies lies in the nonlinear nature of the printability phenomenon. The imaging process involved in the optical pattern transfer techniques used in lithography has a nonlinear functional relationship to the layout patterns on the photomask. Mathematically, using programming like notation, the lithographic imaging process may be expressed as equation 1 below:I(x,y)=Sum {for k=1 to m of|(Tk*U)(x,y)|^2}  [equation 1],where ‘I’ is the intensity of the output image printed on the wafer, (x,y) are the spacial coordinates at which the image intensity is calculated, ‘U’ is the spatial transmission intensity matrix of a given photomask, {Tk}, k=1 to m is the lithographic model. This equation constitutes the discretized formulation of the lithographic imaging based on the Hopkins partially coherent imaging theory. The model {Tk} consists of a set of spacial convolution kernels, which are computed from the Hopkins transmission cross-coefficient (TCC) matrix. The TCC matrix fully describes a given imaging system, which depends on optical parameters such as wavelength of light, lens numerical aperture, the shape of the illuminator, defocus, etc. The model may be further calibrated to capture various process effects such as photoresist, etching, chemical-mechanical polishing, etc. The transmission intensity matrix represents the spacial transmission properties on the mask layout patterns.
Since various printability criteria such as EPE, MEEF, image contrast, etc., are derived from the image intensity, they are also inherently nonlinear with respect to the mask. As a result, printability optimization does not provide sufficient quality, accuracy and efficiency when using linear programming methods.
Thus, it is desirable to have a layout printability optimization system that would overcome the limitations of these existing printability optimization techniques, easily integrate with the IC design infrastructure, produce optimal results within a short amount of time and reduce the need for human intervention.